Conventionally, there has been provided a semiconductor circuit apparatus which compensates the output phase of a variable delay circuit for more than a delay time variable range of the variable delay circuit in such a manner that when the output phase of the variable delay circuit selected as a route of a clock signal differs from the output phase of another variable delay circuit by only one cycle, the semiconductor circuit apparatus switches the operation from the variable delay circuit to another variable delay circuit.
In addition, there has been provided a semiconductor circuit apparatus which avoids excessive tracking of the jitter included in input data by making a majority decision using a majority circuit on the results of phase comparison made by phase comparators.
In addition, there has been provided a synchronization detection circuit which counts the number of continuous errors when synchronization errors occur continuously, and determines that the initially detected synchronizing signal has been erroneously detected when the number of the continuous errors reaches a predetermined number.
The following are reference documents:
[Document 1] Japanese Laid-Open Patent Publication No. 2001-075671,
[Document 2] Japanese Laid-Open Patent Publication No. 2005-033392, and
[Document 3] Japanese Laid-Open Patent Publication No. 2-206070 are examples of related art.